In nonvolatile semiconductor memory devices such as NAND type flash memory, improvement in bit density caused by miniaturization technology is reaching its limit. As a result, development of three-dimensional type memory devices having a plurality of memory transistors (memory cells) stacked in a direction perpendicular to a substrate, is being advanced.
One proposed example of such a three-dimensional type memory device is a stacked type NAND type flash memory employing a vertical transistor to configure the memory transistors. The stacked type NAND type flash memory includes: a memory string configured from a plurality of the memory transistors connected in series in a stacking direction; and a select transistor provided at both ends of the memory string.
Such a stacked type NAND type flash memory has a problem that as the number of memory transistors stacked increases and channel thickness or channel diameter of the memory transistors is reduced, a cell current (channel current) flowing in the memory string is also reduced, whereby execution of an accurate and fast read operation becomes difficult.